Sandip Ray, Ph.D., has received $300k in funding from the National Science Foundation in support of his research in the area of post-silicon validation. The project, “SOCRATES: Post-Silicon Validation of Hardware-Software Interactions,” is a collaboration with researchers at the University of Illinois-Chicago.
The Background
Modern microelectronic systems include considerable low-level software code critical to the system functionality. This software must be ready when the system is shipped and is difficult to modify post deployment. Post-silicon validation involves the use of a fabricated pre-production chip to evaluate whether or not the software works as expected.
Post-silicon software validation is a highly complex and expensive activity requiring significant up-front planning and accounting for the significant associated costs. According to Ray, there has been little research in post-silicon software validation—current research tends to focus on functional and security validation of the underlying hardware. Ray’s project addresses this crucial problem via a comprehensive foundational paradigm and tool suite to streamline post-silicon software validation.
Post-Silicon Validation
The project’s key feature is a unique architecture for observing hardware-software interaction in a silicon platform, methods to generate appropriate test inputs for exercising these interactions, and an objective metric to identify the quality of validation.
The project’s broader impacts and significance include a pathway to derive high assurance in the correctness of modern microelectronics systems that include tightly interacting hardware and software components, as well as the creation of hands-on training modules to enable awareness in the problem for undergraduate and high school students.
The technical insight brought by Ray and his team of researchers at the Rising Lab is that a comprehensive post-silicon validation methodology requires cooperation of three components: an architecture for recording and transporting system events providing observability of the system internals during execution, a test generation methodology that is observability-aware, and a new coverage metric that accounts for the test scenarios being exercised and events being observed.
The project realizes this insight through cooperative application of a novel architecture for collecting and synchronizing hardware-software events and a design automation flow that integrates this architecture with test generation and coverage calculation. The methodology targets validation of open-source System-on-Chip designs as well as emergent commercial systems.